CS GATE 2010 (Test 5)



Tag: cs gate 2010
Q.1
The question below consists of a pair of related words followed by four pairs of words. Select the pair that best expresses the relation in the original pair. Unemployed: Worker
A. fallow: land
B. unaware: sleeper
C. wit: jester
D. renovated:house
Answer : Option A
Explaination / Solution:
No Explaination.


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Topic: Arithmetic Tag: CS GATE 2010
Q.2
Given digits 2,2,3,3,4,4,4,4 how many distinct 4 digit numbers greater than 3000 can be formed?
A. 50
B. 51
C. 52
D. 54
Answer : Option C
Explaination / Solution:
No Explaination.


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Q.3
A system has n resources R0,…,Rn-1, and k processes P0,…..Pk-1. The implementation of the resource request logic of each process Pi. is as follows: 
if (i% 2==0) {
 if (i<n) request Ri;
 if (i+2<n)request Ri+2 ;
}
else {
 if (i<n) request Rn-i ;
 if (i+2<n)request Rn-i-2 ;
}
In which one of the following situations is a deadlock possible?
A. n = 40,k = 26
B. n = 21,k = 12
C. n = 20,k = 10
D. n = 41,k = 19
Answer : Option B
Explaination / Solution:
No Explaination.


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Topic: Databases Tag: CS GATE 2010
Q.4
A relational schema for a train reservation database is given below 
Passenger (pid, pname, age) 
Reservation (pid, cass, tid)

What pids are returned by the following SQL query for the above instance of the tables? 
SELECT pid 
FROM Reservation 
WHERE class ' AC ' AND 
              EXISTS (SELECT * FROM Passenger WHERE age>  65 AND Passenger.pid = Reservation.pid)
A. 1,0
B. 1,2
C. 1,3
D. 1,5
Answer : Option D
Explaination / Solution:
No Explaination.


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Q.5
A main memory unit with a capacity of 4 megabytes is built using 1M×1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is
A. 100 nanoseconds
B. 100*210 nanoseconds
C.  100*220 nanoseconds 
D. 3200*220 nanoseconds 
Answer : Option B
Explaination / Solution:
No Explaination.


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Q.6
The following program consists of 3 concurrent processes and 3 binary semaphores. The semaphores are initialized as S0=1, S1=0, S2=0. 

How many times will process P0 print ‘0’?
A. At least twice
B. Exactly twice
C. Exactly thrice
D. Exactly once
Answer : Option D
Explaination / Solution:
No Explaination.


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Q.7
Let L = {w ∈ (0 + 1)* | w has even number of 1s}, i.e. L is the set of all bit strings with even number of 1s. Which one of the regular expressions below represents L?
A. (0 *10 *1)*
B. 0 * (10 * 10 *) *
C. 0 * (10 * 1 *) * 0 *
D. 0 * 1 (10 * 1) * 10 *
Answer : Option A
Explaination / Solution:
No Explaination.


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Q.8
Let G=(V, E) be a graph. Define  where id is the number of vertices of degree d in G. If S and T are two different trees with ξ(S) = ξ(T), then 
A. |S| = 2|T|
B. |S| = |T| - 1
C. |S| = |T|
D. |S| = |T| + 1
Answer : Option D
Explaination / Solution:
No Explaination.


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Q.9
The cyclomatic complexity of each of the modules A and B shown below is 10. What is the cyclomatic complexity of the sequential integration shown on the right hand side? 

A. 19
B. 21
C. 20
D. 10
Answer : Option D
Explaination / Solution:
No Explaination.


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Q.10
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? 

A. 13
B. 15
C. 17
D. 19
Answer : Option A
Explaination / Solution:
No Explaination.


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