# Analog and Digital Electronics (Test 2)

## Gate Exam : Ee Electrical Engineering

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Topic: Digital Circuits Tag:
Q.1
A low – pass filter with a cut-off frequency of 30Hz is cascaded with a high-pass filter with a cut-off frequency of 20Hz. The resultant system of filters will function as
A. an all-pass filter
B. an all-stop filter
C. an band stop (band-reject) filter
D. a band – pass filter
Explaination / Solution: Workspace
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Q.2
A 10 kHz even-symmetric square wave is passed through a bandpass filter with centre frequency at 30 kHz and 3 dB passband of 6 kHz. The filter output is
A. a highly attenuated square wave at 10kHz
B. nearly zero.
C. a nearly perfect cosine wave at 30kHz.
D. a nearly perfect sine wave at 30kHz.
Explaination / Solution:

10 KHz even symmetric square wave have frequency component present 10KHz, 30KHz, 50KHz, 70KHz [only odd harmonics due to half wave symmetry] Since bandpass filter is contered at 30KHz, 30KHz component will pass through filter output is nearly perfect cosine wave at 10 KHz Cosine in due to reason that signal in even signal.

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Q.3
The circuit shown below is an example of a A. low pass filter.
B. band pass filter.
C. high pass filter.
D. notch filter.
Explaination / Solution: Workspace
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Q.4
The increasing order of speed of data access for the following devices is i. Cache Memory ii. CDROM iii. Dynamic RAM iv. Processor Registers v. Magnetic Tape
A. (v), (ii), (iii), (iv), (i )
B. (v), (ii), (iii), (i), (iv)
C. (ii), (i), (iii), (iv), (v)
D. (v), ( ii), (i) , (iii), (iv)
Explaination / Solution:
No Explaination.

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Q.5
An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped I/O as show in the figure. The address lines A0 and A1 of the 8085 are used by the 8255 chip to decode internally its thee ports and the Control register. The address lines A3 to A as well as the signal are used for address decoding. The range of addresses for which the 8255 chip would get selected is A. F8H - FBH
B. F8GH - FCH
C. F8H - FFH
D. F0H - F7H
Explaination / Solution:  Workspace
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Q.6
In the following circuit, the comparators output is logic “1” if V1 > V2 and is logic "0" otherwise. The D/A conversion is done as per the relation Volts, where b3 (MSB), b1,b2 and b0 (LSB) are the counter outputs. The counter starts from the clear state. The stable reading of the LED displays is
A. 06
B. 07
C. 12
D. 13
Explaination / Solution: and when VADC = 6.5 V (at 1101), the output of AND is zero and the counter stops. The stable output of LED display is 13.

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Q.7
In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = '0'. If the input condition is changed simultaneously to P = Q = '1', the outputs X and Y are A. X = '1', Y = '1'
B. either X = '1', Y = '0' or X = '0', Y = '1'
C. either X = '1', Y = '1' or X = '0', Y = '0'
D. X = '0', Y = '0'
Explaination / Solution:

Unequal propagation delay Case I:                                                              Case II:
Gate 12ns                                                     Gate 11nsec
Gate 21ns                                                     Gate 22nsec Either x = 1, y = 0 or x = 0, y =1

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Q.8
The Boolean expression simplifies to
A. X
B. Y
C. XY
D. X + Y
Explaination / Solution:

Given the Boolean expression We simplify the expression as Workspace
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Q.9
When the output Y in the circuit below is ‘1’, it implies that data has A. changed from 0 to 1
B. changed from 1 to 0
C. changed in either direction
D. not changed
Explaination / Solution:
No Explaination.

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Q.10
The DFT of a vector [a b c d] is the vector [α β γ δ]. Consider the product The DFT of the vector [p q r s] is a scaled version of
A. 2 β2 γ2 δ2]
B. [α β γ δ]
C. [α+β β+δ δ+γ γ+α]
D. [α β γ δ]