# Operating System (Test 4)

## Gate Exam : Cs Computer Science And Information Technology

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Q.1
Consider the following schedule for transactions T1, T2 and T3:
T1                   T2                      T3
Read(X)
Read(Y)
Read(Y)
Write(Y)
Write(X)
Write(X)
Read(X)
Write(X)
Which one of the schedules below is the correct serialization of the above?
A. T1 → T3 → T2
B. T2 → T1 → T3
C. T2 → T3 → T1
D. T3 → T1 → T2
Answer : Option B
Explaination / Solution:
No Explaination.

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Q.2
The following program consists of 3 concurrent processes and 3 binary semaphores. The semaphores are initialized as S0=1, S1=0, S2=0. How many times will process P0 print ‘0’?
A. At least twice
B. Exactly twice
C. Exactly thrice
D. Exactly once
Answer : Option D
Explaination / Solution:
No Explaination.

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Q.3
A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively. When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?
A. 2 nanoseconds
B. 20 nanoseconds
C. 22 nanoseconds
D. 88 nanoseconds
Answer : Option D
Explaination / Solution:
No Explaination.

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Q.4
A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?
A. 222 nanoseconds
B. 888 nanoseconds
C. 902 nanoseconds
D. 968 nanoseconds
Answer : Option B
Explaination / Solution:
No Explaination.

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Q.5
A shared variable x, initialized to zero, is operated on by four concurrent processes W, X, Y, Z as follows. Each of the processes W and X reads x from memory, increments by one, stores it to memory, and then terminates. Each of the processes Y and Z reads x from memory, decrements by two, stores it to memory, and then terminates. Each process before reading x invokes the P operation (i.e., wait) on a counting semaphore S and invokes the V operation (i.e., signal) on the semaphore S after storing x to memory. Semaphore S is initialized to two. What is the maximum possible value of x after all processes complete execution?
A. -2
B. -1
C. 1
D. 2
Answer : Option D
Explaination / Solution:
No Explaination.

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Q.6
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have almost two source operands and one destination operand.
Assume that all variables are dead after this code segment
c = a + b;
d = c * a;
e = c + a;
x = c *c;
if (x > a) {
y = a * a;
}
else {
d = d * d;
e = e * e;
}
Suppose the instruction set architecture of the processor has only two registers. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. What is the minimum number of spills to memory in the compiled code?
A. 0
B. 1
C. 2
D. 3
Answer : Option B
Explaination / Solution:

After applying the code motion optimization the statement d=c*a; and e=c+a; can be moved down to else block as d and e are not used anywhere before that and also value of a and c is not changing. In the above code total number of spills to memory is 1

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Q.7
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have almost two source operands and one destination operand.
Assume that all variables are dead after this code segment
c = a + b;
d = c * a;
e = c + a;
x = c *c;
if (x > a) {
y = a * a;
}
else {
d = d * d;
e = e * e;
}
What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation
A. 3
B. 4
C. 5
D. 6
Answer : Option B
Explaination / Solution: In the above code minimum number of registers needed are = 4

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