Operating System - Online Test
Q1. Consider the methods used by processes P1 and P2 for accessing their critical
sections whenever needed, as given below. The initial values of shared boolean
variables S1 and S2 are randomly assigned.
Which one of the following statements describes the properties achieved?
Answer : Option B
Explaination / Solution:
No Explaination.
Q2. Which of the following statements are true?
I. Shortest remaining time first scheduling may cause starvation
II. Preemptive scheduling may cause starvation
III. Round robin is better than FCFS in terms of response time
Answer : Option B
Explaination / Solution:
No Explaination.
Q3. The program below uses six temporary variables a, b, c, d, e, f.
a = 1
b = 10
c = 20
d = a + b
e = c + d
f = c + e
b = c + e
e = b + f
d = 5 + e
return d + f
Assuming that all operations take their operands from registers, what is the
minimum number of registers needed to execute thi s program without spilling?
Answer : Option C
Explaination / Solution:
No Explaination.
Q4. Consider the following schedule for transactions T1, T2 and T3:
T1 T2 T3
Read(X)
Read(Y)
Read(Y)
Write(Y)
Write(X)
Write(X)
Read(X)
Write(X)
Which one of the schedules below is the correct serialization of the above?
Answer : Option B
Explaination / Solution:
No Explaination.
Q5. The following program consists of 3 concurrent processes and 3 binary
semaphores. The semaphores are initialized as S0=1, S1=0, S2=0.
How many times will process P0 print ‘0’?
Answer : Option D
Explaination / Solution:
No Explaination.
Q6. A computer system has an L1 cache, an L2 cache, and a main memory unit
connected as shown below. The block size in L1 cache is 4 words. The block size
in L2 cache is 16 words. The memory access times are 2 nanoseconds.
20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory
unit respectively.
When there is a miss in L1 cache and a hit in L2 cache, a block is transferred
from L2 cache to L1 cache. What is the time taken for this transfer?
Answer : Option D
Explaination / Solution:
No Explaination.
Q7. A computer system has an L1 cache, an L2 cache, and a main memory unit
connected as shown below. The block size in L1 cache is 4 words. The block size
in L2 cache is 16 words. The memory access times are 2 nanoseconds.
20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory
unit respectively.
When there is a miss in both L1 cache and L2 cache, first a block is transferred
from main memory to L2 cache, and then a block is transferred from L2 cache to
L1 cache. What is the total time taken for these transfers?
Answer : Option B
Explaination / Solution:
No Explaination.
