EC GATE 2007 - Online Test

Q1. In the Op-Amp circuit shown, assume that the diode current follows the equation I = Ise P(V VT). For V= V, V = V, and for V= V, V = V. The relationship between V and V is

Answer : Option D
Explaination / Solution:

Here the inverting terminal is at virtual ground and the current in resistor and diode current is equal i.e. 



Q2. Thefield (in A/m) of a plane wave propagating in free space is given by
The time average power flow density in Watts is
Answer : Option D
Explaination / Solution:



Q3. Consider the Op-Amp circuit shown in the figure. 

The transfer function V(s) Vi(s)
Answer : Option A
Explaination / Solution:




Q4. Consider the Op-Amp circuit shown in the figure. 
If   then the minimum and maximum values of ϕ (in radians) are respectively
Answer : Option C
Explaination / Solution:



Q5. In the Digital-to-Analog converter circuit shown in the figure below, VR = 1V and R = 1kΩ

The voltage V  is
Answer : Option C
Explaination / Solution:
No Explaination.


Q6. The electron and hole concentrations in an intrinsic semiconductor are ni per cm3 at 300 K. Now, if acceptor impurities are introduced with a concentration of NA per cm3 (where N>> ni , the electron concentration per cm3 at 300 K will be
Answer : Option D
Explaination / Solution:

As per mass action law
np = ni
If acceptor impurities are introduces


Q7. In a p n junction diode under reverse biased the magnitude of electric field is maximum at
Answer : Option C
Explaination / Solution:

The electric field has the maximum value at the junction of p n.

Q8. The correct full wave rectifier circuit is
Answer : Option C
Explaination / Solution:



Q9. X = and Y = are two 5-bit binary numbers represented in two’s complement format. The sum of X and Y represented in two’s complement format using 6 bits is
Answer : Option C
Explaination / Solution:

MSB of Y is 1, thus it is negative number and X is positive number

In signed two’s complements from 7 is


Q10. The Boolean function Y = AB + CD is to be realized using only 2 - input NAND gates. The minimum number of gates required is
Answer : Option B
Explaination / Solution:


This is SOP form and we require only 3 NAND gate