Electronics Engineering (Test 3)

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Electronics Engineering
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Q.1
P is a 16-bit signed integer. The 2’s complement representation of P is (F87B)16. The 2’s complement representation of 8*P is 
A. (C3D8)16
B. (187B)16
C. (F878)16
D. (987B)16
Answer : Option A
Explaination / Solution:
No Explaination.


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Q.2
What is the minimal form of the Karnaugh map shown below? Assume that X denotes a don’t care term.


A.
B.
C.
D.
Answer : Option B
Explaination / Solution:



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Q.3
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flops is connected to the input of the T flip-flop and the output of the T Flip-flop connected to the input of the D Flip-flop. 
Initially, both Qand Q1 are set to 1 ( before the 1st clock cycle). The outputs

A. Q1Q0 after the 3rd cycle are 11 and after the  4th cycle are 00 respectively
B. Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively
C. Q1Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively
D. Q1Q0 after the 3rd cycle are 01 and after the 4th cycle are 01 respectively
Answer : Option B
Explaination / Solution:



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Q.4
The state transition diagram for the logic circuit shown is

A.
B.
C.
D.
Answer : Option D
Explaination / Solution:



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Q.5
A Boolean function f(A,B,C,D) = ∏(1,5,12,15) is to be implemented using an 8×1 multiplexer (A is MSB). The inputs ABC are connected to the select inputs S2S1S0 of the multiplexer respectively.
 
Which one of the following options gives the correct inputs to pins 0,1,2,3,4,5,6,7 in order?
A.
B.
C.
D.
Answer : Option B
Explaination / Solution:



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Q.6
The TTL circuit shown in the figure is fed with the waveform X (also shown). All gates have equal propagation delay of 10ns. The output Y of the circuit is

A.
B.
C.
D.
Answer : Option A
Explaination / Solution:
No Explaination.


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Q.7
The circuit diagram of a standard TTL NOT gate is shown in the figure. Vi = 25 V, the modes of operation of the transistors will be 

A. Q1 revere active; Q2 normal active; Q saturation; Q4 cut-off
B. Q1 revere active; Q2 saturation; Q saturation; Q4 cut-off
C. Q1 normal active; Q2 cut-off; Q cut-off; Q4 saturation
D. Q1 saturation; Q2 saturation; Q saturation; Q4 normal active
Answer : Option B
Explaination / Solution:
No Explaination.


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Q.8
Which of the following Boolean Expressions correctly represents the relation between P,Q,R and M1

A. M= (PORQ) XOR R
B. M= (PANDQ) XOR R
C. M= (PNORQ) XOR R
D. M= (PXORQ) XOR R
Answer : Option D
Explaination / Solution:



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Q.9
The Boolean function realized by the logic circuit shown is

A. F = ∑m(0, 1, 3, 5, 9, 10, 14)
B. F = ∑m(2, 3, 5, 7, 8, 12, 13)
C. F = ∑m(1, 2, 4, 5, 11, 14, 15)
D. F = ∑m(2, 3, 5, 7, 8, 9, 12)
Answer : Option D
Explaination / Solution:

Output of the MUX can be written as


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Q.10
A 3-input majority gate is defined by the logic function M(a,b,c) = ab + bc + ca. Which one of the following gates is represented by the function 
A. 3-input NAND gate
B. 3-input XOR gate
C. 3-input NOR gate
D. 3-input XNOR gate
Answer : Option B
Explaination / Solution:

3 input majority gate is given as
M(a,b,c) = ab + bc + ca
We have to obtain 


We obtain truth table for the function as

So, the function is odd number of 1’s detector. This function represent the 3-input XOR gate.

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EEE Electrical and Electronics Engineering