# Analog and Digital Electronics (Test 3)

## Gate Exam : Ee Electrical Engineering

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Analog and Digital Electronics
| Analog Circuits | | Digital Circuits |
Q.1
A portion of the main program to call a subroutine SUB in an 8085 environment is given below. : : LXI D,DISP LP : CALL SUB : It is desired that control be returned to LP+DISP+3 when the RET instruction is executed in the subroutine. The set of instructions that precede the RET instruction in the subroutine are
A.
B.
C.
D.
Explaination / Solution:
No Explaination.

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Q.2
The SOP (sum of products) form of a Boolean function is Σ(0,1,3,7,11), where inputs are A,B,C,D (A is MSB, and D is LSB). The equivalent minimized expression of the function is
A.
B.
C.
D.
Explaination / Solution:

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Q.3
The Boolean expression  simplifies to
A. 1
B.
C. a. b
D. 0
Explaination / Solution:

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Q.4
The complete set of only those Logic Gates designated as Universal Gates is
A. NOT, OR and AND Gates
B. XNOR, NOR and NAND Gate
C. NOR and NAND Gates
D. XOR, NOR and NAND Gates
Explaination / Solution:
No Explaination.

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Q.5
An 8085 assembly language program is given below.
Line 1:   MVI A, B5H
2:   MVI B, OEH
3:   XRI 69H
5:   ANI 9BH
6:   CPI 9FH
7:   STA 3010H
8:   HLT
The contents of the accumulator just execution of the ADD instruction in line 4 will be
A. C3H
B. EAH
C. DCH
D. 69H
Explaination / Solution:

Line 1 : MVI A, B5H ; Move B5H to A
2 : MVI B, 0EH ; Move 0EH to B
3 : XRI 69H      ; [A] XOR 69H and store in A
; Contents of A is CDH
4 : ADDB          ; Add the contents of A to contents of B and
; store in A, contents of A is EAH
5 : ANI 9BH      ; [a] AND 9BH, and store in A,
; Contents of A is 8 AH
6 : CPI 9FH      ; Compare 9FH with the contents of A
; Since 8 AH < 9BH, CY = 1
7 : STA 3010 H  ; Store the contents of A to location 3010 H
8 : HLT               ; Stop
Thus the contents of accumulator after execution of ADD instruction is EAH.

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Q.6
In the following circuit, the comparators output is logic “1” if V1 > V2 and is logic "0" otherwise. The D/A conversion is done as per the relationVolts, where b3 (MSB), b1,b2 and b0 (LSB) are the counter outputs. The counter starts from the clear state.
The magnitude of the error between VDAC and Vin at steady state in volts is
A. 0.2
B. 0.3
C. 0.5
D. 1.0
Explaination / Solution:
No Explaination.

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Q.7
A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are QA QB00,01,10 and 11.

Assume that XIN is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state QA QB = 00 and clocked, after a few clock cycles, it starts cycling through
A. all of the four possible states if XIN = 1
B. three of the four possible states if XIN = 0
C. only two of the four possible states if XIN = 1
D. only two of the four possible states if XIN = 0
Explaination / Solution:

In given diagram

When Xin = 0 2 State
When Xin =1 3 State

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Q.8
What are the counting states (Q1,Q2) for the counter shown in the figure below

A. 11,10,00,11,10,...
B. 01,10,11,00,01...
C. 00,11,01,10,00...
D. 01,10,00,01,10...
Explaination / Solution:

The given circuit is as follows.

The truth table is as shown below. Sequence is 00, 11, 10, 00 ...

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Q.9
The logic function implemented by the circuit below is (ground implies logic 0)

A. F = AND (P, Q)
B. F = OR (P, Q)
C. F = X NOR (P, Q)
D. F = X OR (P, Q)
Explaination / Solution:

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Q.10
In the circuit shown below, Q1 has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If Vcc is +5 V, X and Y are digital signals with 0 V as logic 0 and Vcc as logic 1, then the Boolean expression for Z is

A. XY
B.
C.
D.