Analog and Digital Electronics

Analog and Digital Electronics

Analog and Digital Electronics
| Digital Circuits | | Analog Circuits |
Q.1
The output Y of the logic circuit given below is

A. 0
B. 1
C. X
D.
Answer : Option A
Explaination / Solution:



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Q.2
Which of the following is an invalid state in an 8-4-2-1. Binary Coded Decimal counter
A. 1 0 0 0
B. 1 0 0 1
C. 0 0 1 1
D. 1 1 0 0
Answer : Option D
Explaination / Solution:

In binary coded decimal (BCD) counter the valid states are from 0 to 9 only in binary system 0000 to 1001 only. So, 1100 in decimal it is 12 which is invalid state in BCD counter.

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Q.3
The output expression for the Karnaugh map shown below is

A.
B.
C.
D.
Answer : Option B
Explaination / Solution:



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Q.4
The following Karnaugh map represent a function F.

Which of the following circuits is a realization of the above function F?
A.
B.
C.
D.
Answer : Option D
Explaination / Solution:
No Explaination.


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Q.5
For the circuit shown, the counter state (Q1Q0) follows the sequence

A. 00,01,10,11,00
B. 00,01,10,00,01
C. 00,01,11,00,01
D. 00,10,11,00,10
Answer : Option A
Explaination / Solution:



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Q.6
For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible. Which of the following statements is true

A. Q goes to 1 at the CLK transition and stays at 1
B. Q goes to 0 at the CLK transition and stays 0
C. Q goes to 1 at the CLK tradition and goes to 0 when D goes to 1
D. Q goes to 0 at the CLK transition and goes to 1 when D goes to 1
Answer : Option A
Explaination / Solution:
No Explaination.


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Q.7
The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 μs, then the number of T-states needed for executing the instruction is
A. 1
B. 6
C. 7
D. 8
Answer : Option C
Explaination / Solution:



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Q.8
What are the minimum number of 2- to -1 multiplexers required to generate a 2- input AND gate and a 2- input Ex-OR gate
A. 1 and 2
B. 1 and 3
C. 1 and 1
D. 2 and 2
Answer : Option A
Explaination / Solution:

The AND gate implementation by 2:1 mux is as follows


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Q.9
The output Y in the circuit below is always ‘1’ when

A. two or more of the inputs P, Q, R are ‘0’
B. two or more of the inputs P, Q, R are ‘1’
C. any odd number of the inputs P, Q, R is ‘0’
D. any odd number of the inputs P, Q, R is ‘1’
Answer : Option B
Explaination / Solution:

The given circuit is shown below:

If any two or more inputs are ‘1’ then output y will be 1.

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Q.10
In an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?
A. For POP, the data transceivers remain in the same direction as for instruction fetch (memory to processor), whereas for PUSH their direction has to be reversed
B. Memory write operations are slower than memory read operations in an 8085 based system.
C. The stack pointer needs to be pre-decremented before writing registers in a PUSH, whereas a POP operation uses the address already in the stack pointer.
D. Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.
Answer : Option C
Explaination / Solution:

In push operation 3 cycles involved: 6T+3T+3T = 127
POP operation 3 cycle involved: 4T+3T+3T = 107
So in the opcode fetch cycle 2T states are extra in case of push compared to POP and this is needed to decrement the SP.

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