Electronic Devices (Test 5)

Gate Exam : Ec Electronics And Communication Engineering

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Electronic Devices

Electronic Devices
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Q.1
For the circuit with ideal diodes shown in the figure, the shape of the output (Voutfor the given sine wave input (Vinwill be


A.
B.
C.
D.
Answer : Option C
Explaination / Solution:


For positive half A1, we have

Vout = -  Vin
For negative half A2, both diode will be OFF. 
So,  Vout = 0
Hence, the output is obtained as


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Q.2
The figure shows the high-frequency capacitance - voltage characteristics of Metal/Sio2/silicon (MOS) capacitor having an area of 1 × 10-4 cm2. Assume that the permittivities (ε0εr) of silicon and Sio are 1 × 10-12 F/cm and 3.5 × 10-13 F/ cm respectively.
The maximum depletion layer width in silicon is
A. 0.143 μm
B. 0.857 μm
C. 1 μm
D. 1.143 μm
Answer : Option B
Explaination / Solution:




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Q.3
If fixed positive charges are present in the gate oxide of an n-channel enhancement type MOSFET, it will lead to
A. a decrease in the threshold voltage
B. channel length modulation
C. an increase in substrate leakage current
D. an increase in accumulation capacitance
Answer : Option A
Explaination / Solution:

If fixed positive charges are present is the gate oxide of an n-channel enhancement type MOSFET, it will lead to a decrease in the threshold voltage.

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Q.4
The doping concentrations on the p-side and n-side of a silicon diode are 1 × 1016 cm-3 and 1 × 1017 cm-3, respectively. A forward bias of 0 3. V is applied to the diode. At T = 300 K, the intrinsic carrier concentration of silicon ni = 1.5 × 1010 cm-3 and (kT/q) = 26 mV.  The electron concentration at the edge of the depletion region on the p-side is
A. 2.3 × 109 cm-3
B.  1 × 1016 cm-3
C. 1 × 1017 cm-3
D. 2.25 × 106 cm-3
Answer : Option A
Explaination / Solution:

Given the doping concentration on p-side
NA = 1 × 1016 cm-3
V = 0.3 V
Intrinsic carrier concentration,

So, the equilibrium electron concentration on the p-side is


Therefore, the electron at the edge of the depletion region on the p-side is obtained as


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Q.5
Two identical NMOS transistors M1 and M2 are connected as shown below. Vbias is chosen so that both transistors are in saturation. The equivalent gm of the pair is defied to be  at constant Vout 
The equivalent gm of the pair is

A.  the sum of individual gm's of the transistors
B.  the product of individual gm’s of the transistors 
C.  nearly equal to the gm of M1
D.  nearly equal to gm/g0 of M2
Answer : Option C
Explaination / Solution:
No Explaination.


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Q.6
For small increase in VG beyond 1V, which of the following gives the correct description of the region of operation of each MOSFET
A. Both the MOSFETs are in saturation region
B. Both the MOSFETs are in triode region
C. n-MOSFETs is in triode and p -MOSFET is in saturation region
D. n- MOSFET is in saturation and p -MOSFET is in triode region
Answer : Option D
Explaination / Solution:

For small increase in VG beyond 1 V the n - channel MOSFET goes into saturation as VGS + ive and p - MOSFET is always in active region or triode region.

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Q.7
The full form of the abbreviations TTL and CMOS in reference to logic families are
A. Triple Transistor Logic and Chip Metal Oxide Semiconductor
B. Tristate Transistor Logic and Chip Metal Oxide Semiconductor
C. Transistor Transistor Logic and Complementary Metal Oxide Semiconductor
D. Tristate Transistor Logic and Complementary Metal Oxide Silicon
Answer : Option C
Explaination / Solution:

TTL -> Transistor - Transistor logic CMOS -> Complementary Metal Oxide Semi-conductor

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Q.8
At room temperature, a possible value for the mobility of electrons in the inversion layer of a silicon n-channel MOSFET is
A.

450 cm2/V-s

B. 1359 cm2/V-s
C. 1800 cm2/V-s
D. 3600 cm2/V-s
Answer : Option A
Explaination / Solution:

At room temperature mobility of electrons for Si sample is given μn = 1350 cm2/V-s For an n-channel MOSFET to create an inversion layer of electrons, a large positive gate voltage is to be applied. Therefore, induced electric field increases and mobility decreases.
So, Mobility μn <1350 cm2/V-s for n-channel MOSFET


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Q.9
For a N -point FET algorithm N = 2m which one of the following statements is TRUE ?
A. It is not possible to construct a signal flow graph with both input and output in normal order
B. The number of butterflies in the mth stage in N/m
C. In-place computation requires storage of only 2N data
D. Computation of a butterfly requires only one complex multiplication.
Answer : Option D
Explaination / Solution:

For an N-point FET algorithm butterfly operates on one pair of samples and involves two complex addition and one complex multiplication.

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Q.10
Compared to a p-n junction with NA  = ND = 10-14/cm3, which one of the following statements is TRUE for a p-n junction with NA  = ND = 10-20/cm3?
A. Reverse breakdown voltage is lower and depletion capacitance is lower
B. Reverse breakdown voltage is higher and depletion capacitance is lower
C. Reverse breakdown voltage is lower and depletion capacitance is higher
D. Reverse breakdown voltage is higher and depletion capacitance is higher
Answer : Option C
Explaination / Solution:

Reverse bias breakdown or Zener effect occurs in highly doped PN junction through tunneling mechanism. In a highly doped PN junction, the conduction and valence bands on opposite sides of the junction are sufficiently close during reverse bias that electron may tunnel directly from the valence band on the p-side into the conduction band on n-side.
Breakdown voltage 
So, breakdown voltage decreases as concentration increases
Depletion capacitance

Depletion capacitance increases as concentration increases

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EC Electronics and Communication Engineering