# Electronic Devices (Test 1)

## Gate Exam : Ec Electronics And Communication Engineering

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Q.1
Group I lists four different semiconductor devices. match each device in Group I with its charactecteristic property in Group II
Group-I                                      Group-II
(P) BJT                                       (1) Population iniversion
(Q) MOS capacitor                     (2) Pinch-off voltage
(R) LASER diode                        (3) Early effect
(S) JFET                                     (4) Flat-band voltage
A. P - 3, Q - 1, R - 4, S - 2
B. P - 1, Q - 4, R - 3, S - 2
C. P - 3, Q - 4, R - 1, S - 2
D. P - 3, Q - 2, R - 1, S - 4
Explaination / Solution:

In BJT as the B-C reverse bias voltage increases, the B-C space charge region width increases which xB (i.e. neutral base width) > A change in neutral base width will change the collector current. A reduction in base width will causes the gradient in minority carrier concentration to increase, which in turn causes an increased in the diffusion current. This effect si known as base modulation as early effect.
In JFET the gate to source voltage that must be applied to achieve pinch off voltage is described as pinch off voltage and is also called as turn voltage or threshold voltage.
In LASER population inversion occurs on the condition when concentration of electrons in one energy state is greater than that in lower energy state, i.e. a non equilibrium condition.
In MOS capacitor, flat band voltage is the gate voltage that must be applied to create flat ban condition in which there is no space charge region in semiconductor under oxide.
Therefore
BJT : Early effect
MOS capacitor : Flat-band voltage
LASER diode : Population inversion
JFET : Pinch-off voltage

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Q.2
In the circuit below, the diode is ideal. The voltage V is given by A. min (Vi,1)
B. max (Vi,1)
C. min (-Vi,1)
D. max (-Vi,1)
Explaination / Solution:

Let diode be OFF. In this case 1 A current will flow in resistor and voltage across resistor will be V = 1.V
Diode is off, it must be in reverse biased, therefore
Vi- 1 > 0 " Vi > 1
Thus for Vi > 1 diode is off and V = 1V
Option (B) and (C) doesn’t satisfy this condition.
Let Vi < 1. In this case diode will be on and voltage across diode will be zero and
V = Vi
Thus V = min(Vi,1)

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Q.3
The figure shows the high-frequency capacitance - voltage characteristics of Metal/Sio2/silicon (MOS) capacitor having an area of 1 × 10-4 cm2. Assume that the permittivities (ε0εr) of silicon and Sio are 1 × 10-12 F/cm and 3.5 × 10-13 F/ cm respectively. Consider the following statements about the C − V characteristics plot :
S1 : The MOS capacitor has as n-type substrate
S2 : If positive charges are introduced in the oxide, the C − V polt will shift to the left.
Then which of the following is true?

A. Both S1 and S2 are true
B. S1 is true and S2 is false
C. S1 is false and S2 is true
D. Both S1 and S2 are false
Explaination / Solution:

Depletion region will not be formed if the MOS capacitor has n type substrate but from C-V characteristics, C reduces if V is increased. Thus depletion region must be formed. Hence S1 is false If positive charges is introduced in the oxide layer, then to equalize the effect the applied voltage V must be reduced. Thus the C − V plot moves to the left. Hence S2 is true.

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Q.4
In the following limiter circuit, an input voltage Vi = 10 sin100πt is applied. Assume that the diode drop is 0.7 V when it is forward biased. When it is forward biased. The zener breakdown voltage is 6.8 V
The maximum and minimum values of the output voltage respectively are A. 6.1V, - 0.7 V
B. 0.7 V, - 7.5 V
C. 7.5 V, - 0.7 V
D. 7.5 V, - 7.5 V
Explaination / Solution:
No Explaination.

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Q.5
For the circuit shown in the following figure, transistor M1 and M2 are identical NMOS transistors. Assume the M2 is in saturation and the output is unloaded. The current Ix is related to Ibias as

A. B. C. D. Explaination / Solution: Workspace
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Q.6
Silicon is doped with boron to a concentration of 4 × 1017 atoms cm3. Assume the intrinsic carrier concentration of silicon to be 1.5 × 1010/cmand the value of kT/q to be 25 mV at 300 K. Compared to undopped silicon, the fermi level of doped silicon
A. goes down by 0.31 eV
B. goes up by 0.13 eV
C. goes down by 0.427 eV
D. goes up by 0.427 eV
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Topic: Electronic Devices Tag:
Q.7
Estimate the output voltage V0 for VG = 1.5 V. [Hints : Use the appropriate current-voltage equation for each MOSFET, based on the answer to Q.57]
A. B. C. D. Explaination / Solution:

Consider for CMOS circuit shown, where the gate voltage v0 of the n-MOSFET is increased from zero, while the gate voltage of the p -MOSFET is kept constant at 3 V. Assume, that, for both transistors, the magnitude of the threshold voltage is 1 V and the product of the trans-conductance parameter is 1mA. V-2 Workspace
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Q.8
In a MOSFET operating in the saturation region, the channel length modulation effect causes
A. an increase in the gate-source capacitance
B. a decrease in the transconductance
C. a decrease in the unity-gain cutoff frequency
D. a decrease in the output resistance
Explaination / Solution:

In a MOSFET operating in the saturation region, the channel length modulation effect causes a decrease in output resistance.

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Q.9
Thin gate oxide in a CMOS process in preferably grown using
A. wet oxidation
B. dry oxidation
C. epitaxial oxidation
D. ion implantation
Explaination / Solution:

Dry oxidation is used to achieve high quality oxide growth.

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Q.10
In the circuit shown below, for the MOS transistors, and the threshold voltage VT = 1 V. The voltage Vx at the source of the upper transistor is A. 1 V
B. 2 V
C. 3 V
D. 3.67 V
Explaination / Solution:

Given circuit is shown below. For transistor M2, Since thus M2 is in saturation. By assuming M1 to be in saturation we have Taking positive root,  Thus our assumption is true and Vx = 3 V.

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