Digital Circuits (Test 5)

Gate Exam : Ec Electronics And Communication Engineering

Digital Circuits

Digital Circuits
| Digital Circuits |
Q.1
The circuit diagram of a standard TTL NOT gate is shown in the figure. Vi = 25 V, the modes of operation of the transistors will be 

A. Q1 revere active; Q2 normal active; Q saturation; Q4 cut-off
B. Q1 revere active; Q2 saturation; Q saturation; Q4 cut-off
C. Q1 normal active; Q2 cut-off; Q cut-off; Q4 saturation
D. Q1 saturation; Q2 saturation; Q saturation; Q4 normal active
Answer : Option B
Explaination / Solution:
No Explaination.


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Topic: Digital Circuits Tag:
Q.2
A low – pass filter with a cut-off frequency of 30Hz is cascaded with a high-pass filter with a cut-off frequency of 20Hz. The resultant system of filters will function as
A. an all-pass filter
B. an all-stop filter
C. an band stop (band-reject) filter
D. a band – pass filter
Answer : Option D
Explaination / Solution:



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Q.3
A 3-input majority gate is defined by the logic function M(a,b,c) = ab + bc + ca. Which one of the following gates is represented by the function 
A. 3-input NAND gate
B. 3-input XOR gate
C. 3-input NOR gate
D. 3-input XNOR gate
Answer : Option B
Explaination / Solution:

3 input majority gate is given as
M(a,b,c) = ab + bc + ca
We have to obtain 


We obtain truth table for the function as

So, the function is odd number of 1’s detector. This function represent the 3-input XOR gate.

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Q.4
In the Digital-to-Analog converter circuit shown in the figure below, VR = 1V and R = 1kΩ

The current i is
A. 31.25μA
B. 62.5μA
C. 125μA
D. 250μA
Answer : Option B
Explaination / Solution:




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Q.5
What are the minimum number of 2- to -1 multiplexers required to generate a 2- input AND gate and a 2- input Ex-OR gate
A. 1 and 2
B. 1 and 3
C. 1 and 1
D. 2 and 2
Answer : Option A
Explaination / Solution:

The AND gate implementation by 2:1 mux is as follows


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Q.6
The output F in the digital logic circuit shown in the figure is

A.
B.
C.
D.
Answer : Option A
Explaination / Solution:

In the logic circuit, the two inputs to the output AND gate are

So, we have the output



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Q.7
The Boolean expression  simplifies to
A.
B.
C.
D. AB + BC
Answer : Option A
Explaination / Solution:



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Q.8
Which of the following Boolean Expressions correctly represents the relation between P,Q,R and M1

A. M= (PORQ) XOR R
B. M= (PANDQ) XOR R
C. M= (PNORQ) XOR R
D. M= (PXORQ) XOR R
Answer : Option D
Explaination / Solution:



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Q.9
For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible. Which of the following statements is true

A. Q goes to 1 at the CLK transition and stays at 1
B. Q goes to 0 at the CLK transition and stays 0
C. Q goes to 1 at the CLK tradition and goes to 0 when D goes to 1
D. Q goes to 0 at the CLK transition and goes to 1 when D goes to 1
Answer : Option A
Explaination / Solution:
No Explaination.


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Q.10
The second harmonic component of the periodic waveform given in the figure has an amplitude of

A. 0
B. 1
C. 2/π
D. √5
Answer : Option A
Explaination / Solution:
No Explaination.


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EC Electronics and Communication Engineering