The minimum number of D flip-flops needed to design a mod-258 counter is

**A. ** 9

**B. ** 8

**C. ** 512

**D. ** 258

**Answer : ****Option A**

**Explaination / Solution: **

2^{n }≥ 258 ⇒ n = 9

2

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Consider the Boolean operator # with the following properties:

**A. **

**B. **

**C. **

**D. **

**Answer : ****Option A**

**Explaination / Solution: **

No Explaination.

Then x # y is equivalent to

No Explaination.

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Consider the following circuit involving three D-type flip-flops used in a certain
type of counter configuration.

**A. ** 3

**B. ** 4

**C. ** 5

**D. ** 6

**Answer : ****Option C**

**Explaination / Solution: **

If all the flip-flops were reset to 0 at power on, what is the total number of
distinct outputs (states) represented by PQR generated by the counter?

So Total number of distinct outputs is 4

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Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

**A. ** 000

**B. ** 001

**C. ** 010

**D. ** 011

**Answer : ****Option D**

**Explaination / Solution: **

From the Table Shown in the explanation of question 50, if first state is 010 next State is 011

If at some instance prior to the occurrence of the clock edge, P. Q and R have a
value 0, 1 and 0 respectively, what shall be the value of PQR after the clock
edge?

From the Table Shown in the explanation of question 50, if first state is 010 next State is 011

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Consider the two cascaded 2-to-1 multiplexers as shown in the figure.

**A. **

**B. **

**C. **

**D. **

**Answer : ****Option D**

**Explaination / Solution: **

The minimal sum of products form of the output X is

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Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flops is connected to the input of the T flip-flop and the output of the T Flip-flop connected to the input of the D Flip-flop.

**A. ** Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 00 respectively

**B. ** Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively

**C. ** Q1Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively

**D. ** Q1Q0 after the 3rd cycle are 01 and after the 4th cycle are 01 respectively

**Answer : ****Option B**

**Explaination / Solution: **

Initially, both Q_{0 }and Q_{1} are set to 1 ( before the 1^{st} clock cycle). The outputs

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The decimal value 0.5 in IEEE single precision floating point representation has

**A. ** fraction bits of 000…000 and exponent value of 0

**B. ** fraction bits of 000…000 and exponent value of -1

**C. ** fraction bits of 100…000 and exponent value of 0

**D. ** no exact representation

**Answer : ****Option B**

**Explaination / Solution: **

(0.5)_{10} = (1.0)_{2} × 2^{-1}

So, exponent = -1 and fraction is 000 - - - 000Workspace

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The truth table

**A. ** X

**B. ** X + Y

**C. ** X ⊕Y

**D. ** Y

**Answer : ****Option A**

**Explaination / Solution: **

XY'+ XY = X(Y'+ Y) = X

represents the Boolean function

XY'+ XY = X(Y'+ Y) = X

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Consider the set of strings on {0,1} in which, every substring of 3 symbols has at most two
zeros. For example, 001110 and 011001 are in the language, but 100010 is not. All strings of
length less than 3 are also in the language. A partially completed DFA that accepts this
language is shown below.

**A. **

**B. **

**C. **

**D. **

**Answer : ****Option D**

**Explaination / Solution: **

The complete DFA is

The missing arcs in the DFA are

The complete DFA is

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What is the minimal form of the Karnaugh map shown below? Assume that X denotes a don’t
care term.

**A. **

**B. **

**C. **

**D. **

**Answer : ****Option B**

**Explaination / Solution: **

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**Preparation Study Material**- Digital Electronics (Study/Preparation)
- Digital Logic Circuits (Study/Preparation)
- Computer Architecture (Study/Preparation)
- Programming and Data Structures I (Study/Preparation)
- Programming and Data Structure II (Study/Preparation)
- Database Management Systems (Study/Preparation)
- Computer Networks (Study/Preparation)
- Operating Systems (Study/Preparation)
- Software Engineering (Study/Preparation)
- Theory of Computation (Study/Preparation)
- Design and Analysis of Algorithms (Study/Preparation)
- Compiler Design (Study/Preparation)

- Engineering Mathematics (Practise Test)
- Digital Logic (Practise Test)
- Computer Organization and Architecture (Practise Test)
- Programming and Data Structures (Practise Test)
- Algorithms (Practise Test)
- Theory of Computation (Practise Test)
- Compiler Design (Practise Test)
- Operating System (Practise Test)
- Databases (Practise Test)
- Computer Networks (Practise Test)