Digital Logic (Test 2)

Gate Exam : Cs Computer Science And Information Technology

Digital Logic

Digital Logic
| Digital Logic |
Q.1
The minimum number of D flip-flops needed to design a mod-258 counter is
A. 9
B. 8
C. 512
D. 258
Answer : Option A
Explaination / Solution:

2≥ 258 ⇒ n = 9 

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Q.2
 Consider the Boolean operator # with the following properties:
  Then x # y is equivalent to
A.
B.
C.
D.
Answer : Option A
Explaination / Solution:
No Explaination.


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Q.3
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. 

If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by PQR generated by the counter? 
A. 3
B. 4
C. 5
D. 6
Answer : Option C
Explaination / Solution:


So Total number of distinct outputs is 4 

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Q.4
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. 
If at some instance prior to the occurrence of the clock edge, P. Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
A. 000
B. 001
C. 010
D. 011
Answer : Option D
Explaination / Solution:

From the Table Shown in the explanation of question 50, if first state is 010 next State is 011

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Q.5
Consider the two cascaded 2-to-1 multiplexers as shown in the figure.

The minimal sum of products form of the output X is  
A.
B.
C.
D.
Answer : Option D
Explaination / Solution:



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Q.6
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flops is connected to the input of the T flip-flop and the output of the T Flip-flop connected to the input of the D Flip-flop. 
Initially, both Qand Q1 are set to 1 ( before the 1st clock cycle). The outputs

A. Q1Q0 after the 3rd cycle are 11 and after the  4th cycle are 00 respectively
B. Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively
C. Q1Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively
D. Q1Q0 after the 3rd cycle are 01 and after the 4th cycle are 01 respectively
Answer : Option B
Explaination / Solution:



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Q.7
The decimal value 0.5 in IEEE single precision floating point representation has
A. fraction bits of 000…000 and exponent value of 0
B. fraction bits of 000…000 and exponent value of -1
C. fraction bits of 100…000 and exponent value of 0
D. no exact representation
Answer : Option B
Explaination / Solution:

(0.5)10 =  (1.0)2 × 2-1
So, exponent = -1 and fraction is 000 - - - 000

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Q.8
 The truth table

represents the Boolean function
A. X
B. X + Y
C. X ⊕Y
D. Y
Answer : Option A
Explaination / Solution:

XY'+ XY = X(Y'+ Y) = X

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Q.9
Consider the set of strings on {0,1} in which, every substring of 3 symbols has at most two zeros. For example, 001110 and 011001 are in the language, but 100010 is not. All strings of length less than 3 are also in the language. A partially completed DFA that accepts this language is shown below.

The missing arcs in the DFA are
A.
B.
C.
D.
Answer : Option D
Explaination / Solution:

The complete DFA is


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Q.10
What is the minimal form of the Karnaugh map shown below? Assume that X denotes a don’t care term.


A.
B.
C.
D.
Answer : Option B
Explaination / Solution:



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CS Computer Science and Information Technology