# Computer Organization and Architecture (Test 2)

## Gate Exam : Cs Computer Science And Information Technology

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Q.1
Which of the following is NOT desired in a good Software Requirement Specifications (SRS) document?
A. Functional Requirements
B. Non Functional Requirements
C. Goals of Implementation
D. Algorithms for Software Implementation
Explaination / Solution:
No Explaination.

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Q.2
Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure. What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?
A. 4.0
B. 2.5
C. 1.1
D. 3.0
Explaination / Solution:

(5 + 6 + 11 + 8) / (11 + 1) = 30 / 12 = 2.5

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Q.3
An 8KB direct mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following. 1 Valid bit 1 Modified bit As many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store metadata (tags) for the cache?
A. 4864 bits
B. 6144bits
C. 6656bits
D. 5376bits
Explaination / Solution: Required answer =256 × (19 + 2) = 5376 bits

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Q.4
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.
Initialize the count to 500
LOOP: Load a byte from device
Decrement the count
If count != 0 go to LOOP
Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.
The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.
What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
A. 3.4
B. 4.4
C. 5.1
D. 6.7
Explaination / Solution:

No. of clock cycles required by using load-store approach = 2 + 500 × 7 = 3502 and that of by using DMA = 20 + 500 × 2 = 1020 Required speed up = 3502/1020 = 3.4

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Q.5
Consider a carry look ahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is
A. Θ(1)
B. Θ(log(n))
C. Θ(√n)
D. Θ(n)
Explaination / Solution:
No Explaination.

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Q.6
Register renaming is done is pipelined processors
A. as an alternative to register allocation at compile time
C. to handle certain kinds of hazards
D. as part of address translation
Explaination / Solution:

Register renaming is done to eliminate WAR/WAW hazards.

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Q.7
When two 8-bit numbers A7....A0 and B7.....B0 in 2’s complement representation (with A0 and B0 as the least significant bits ) are added using a ripple-carry adder, the sum bits obtained are S7….S0 and the carry bits are C7….C0. An overflow is said to have occurred if
A. the carry bit C7 is 1
B. all the carry bits (C7….C0) are 1
C. D. Explaination / Solution:

Overflow flag indicates an over flow condition for a signed operation. Some points to
remember in a signed operation:
* MSB is always reserved to indicate sign of the number.
* Negative numbers are represented in 2’s – complement.
* An overflow results in invalid operation.
2's complement overflow rules:
* If the sum of two positive numbers yields a negative result, the sum has- overflowed.
* If the sum of two negative number yields a positive result, the sum has overflowed.
* Otherwise, the sum has not overflowed.
Overflow for signed numbers occurs when the carry-in into the MSB (most significant bit) is
not equal to carry-out. Conveniently, an XOR-operation on these two bits can quickly
determine if an overflow condition exists.

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Q.8
A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is
A. 11
B. 14
C. 16
D. 27
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Q.9
A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory is
A. 160 Kbits
B. 136 Kbits
C. 40 Kbits
D. 32 Kbits
Explaination / Solution:

TAG controller maintains 16 + 4 = 20 bits for every block
Hence, size of cache tag directory = 20 × 213 bits =160 K bits

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Q.10
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? A. 13
B. 15
C. 17
D. 19